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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-02-14 17:50:56 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-21 16:07:00 +0000 |
| commit | 873b73c0c891ec20adacc7bd1ae789294334d675 (patch) | |
| tree | b19b132054da9f873b9ff37e25b99f139a674e13 /target/arm/helper.c | |
| parent | b830a5ee82e66f54697dcc6450fe9239b7412d13 (diff) | |
| download | focaccia-qemu-873b73c0c891ec20adacc7bd1ae789294334d675.tar.gz focaccia-qemu-873b73c0c891ec20adacc7bd1ae789294334d675.zip | |
target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers
Enforce a convention that an isar_feature function that tests a 32-bit ID register always has _aa32_ in its name, and one that tests a 64-bit ID register always has _aa64_ in its name. We already follow this except for three cases: thumb_div, arm_div and jazelle, which all need _aa32_ adding. (As noted in the comment, isar_feature_aa32_fp16_arith() is an exception in that it currently tests ID_AA64PFR0_EL1, but will switch to MVFR1 once we've properly implemented FP16 for AArch32.) Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200214175116.9164-2-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 8d0f6eca27..9c02d5d6b8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7396,7 +7396,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, lpae_cp_reginfo); } - if (cpu_isar_feature(jazelle, cpu)) { + if (cpu_isar_feature(aa32_jazelle, cpu)) { define_arm_cp_regs(cpu, jazelle_regs); } /* Slightly awkwardly, the OMAP and StrongARM cores need all of |