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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-10-08 14:55:02 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-10-08 14:55:02 +0100 |
| commit | 9516d7725ec1deaa6ef5ccc5a26d005650d6c524 (patch) | |
| tree | fbc8abd477721e042ad4a7cc2d40df52c5f84fb2 /target/arm/helper.c | |
| parent | e5ae4d0c063fbcca4cbbd26bcefbf1760cfac2aa (diff) | |
| download | focaccia-qemu-9516d7725ec1deaa6ef5ccc5a26d005650d6c524.tar.gz focaccia-qemu-9516d7725ec1deaa6ef5ccc5a26d005650d6c524.zip | |
target/arm: Define ID_AA64ZFR0_EL1
Given that the only field defined for this new register may only be 0, we don't actually need to change anything except the name. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 5e721a6527..050f3d444c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5018,9 +5018,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, + /* At present, only SVEver == 0 is defined anyway. */ .resetvalue = 0 }, { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, |