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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-07-14 14:23:01 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-18 13:20:13 +0100 |
| commit | 988cc1909f2895cb751fc9cc83ba51938be02183 (patch) | |
| tree | 72731a3f0eaba947d83ff7af6c1e57cec45cd7de /target/arm/helper.c | |
| parent | afbb181c2deb4584666be17adfbc49532fc90ace (diff) | |
| download | focaccia-qemu-988cc1909f2895cb751fc9cc83ba51938be02183.tar.gz focaccia-qemu-988cc1909f2895cb751fc9cc83ba51938be02183.zip | |
target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t
Change the representation of the VSTCR_EL2 and VTCR_EL2 registers in the CPU state struct from struct TCR to uint64_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220714132303.1287193-6-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 7461d4091e..ea541e4b0c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5413,9 +5413,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, .access = PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ + /* no .writefn needed as this can't cause an ASID change */ .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, { .name = "VTTBR", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 6, .crm = 2, |