summary refs log tree commit diff stats
path: root/target/arm/helper.c
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2022-06-20 10:51:52 -0700
committerPeter Maydell <peter.maydell@linaro.org>2022-06-27 11:18:17 +0100
commita3637e8882f9dbb00036ff77a88b841bd2580900 (patch)
treeed5b8dda8291d86f3df4abbe721731945344ab72 /target/arm/helper.c
parentd5b1223ac1ddf8f706f5e6feaaa526df8287f8b1 (diff)
downloadfocaccia-qemu-a3637e8882f9dbb00036ff77a88b841bd2580900.tar.gz
focaccia-qemu-a3637e8882f9dbb00036ff77a88b841bd2580900.zip
target/arm: Add PSTATE.{SM,ZA} to TB flags
These are required to determine if various insns
are allowed to issue.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
-rw-r--r--target/arm/helper.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bbd04fbd67..e06c054c3d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11335,6 +11335,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
     }
     if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
         DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el));
+        if (FIELD_EX64(env->svcr, SVCR, SM)) {
+            DP_TBFLAG_A64(flags, PSTATE_SM, 1);
+        }
+        DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
     }
 
     sctlr = regime_sctlr(env, stage1);