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authorRichard Henderson <richard.henderson@linaro.org>2025-09-25 17:11:27 -0700
committerPeter Maydell <peter.maydell@linaro.org>2025-10-07 11:26:10 +0100
commitaf95e2aaa0b00615728834a79de5c827158b3d9a (patch)
treef1cf8fe197a39a86b7b56ee3dc4c9da39d6060ca /target/arm/helper.c
parente2c25b123d48a9bb2d723f19a595914690e348b0 (diff)
downloadfocaccia-qemu-af95e2aaa0b00615728834a79de5c827158b3d9a.tar.gz
focaccia-qemu-af95e2aaa0b00615728834a79de5c827158b3d9a.zip
target/arm: Enable FEAT_RME_GPC2 bits in gpccr_write
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20250926001134.295547-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
-rw-r--r--target/arm/helper.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 792a47a9c5..b7bf45afc1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4933,6 +4933,11 @@ static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK |
         R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK;
 
+    if (cpu_isar_feature(aa64_rme_gpc2, env_archcpu(env))) {
+        rw_mask |= R_GPCCR_APPSAA_MASK | R_GPCCR_NSO_MASK |
+                   R_GPCCR_SPAD_MASK | R_GPCCR_NSPAD_MASK | R_GPCCR_RLPAD_MASK;
+    }
+
     env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask);
 }