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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-10 14:32:35 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-10 14:32:35 +0100 |
| commit | bfe43e3d14687f2149451f278671c2c552d96b0a (patch) | |
| tree | b560e74a6212b7c63088a6ef898d1f79020ed8ac /target/arm/helper.c | |
| parent | 284ad5e70c41e02553aeb2c1eaf4e828499cb315 (diff) | |
| download | focaccia-qemu-bfe43e3d14687f2149451f278671c2c552d96b0a.tar.gz focaccia-qemu-bfe43e3d14687f2149451f278671c2c552d96b0a.zip | |
target/arm: Adjust format test in scr_write
Because reset always initializes the AA64 version, SCR_EL3, test the mode of EL3 instead of the type of the cpreg. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609214657.1217913-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index b95aa53474..ff9f9fe6ee 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1738,12 +1738,14 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) uint32_t valid_mask = 0x3fff; ARMCPU *cpu = env_archcpu(env); - if (ri->state == ARM_CP_STATE_AA64) { - if (arm_feature(env, ARM_FEATURE_AARCH64) && - !cpu_isar_feature(aa64_aa32_el1, cpu)) { - value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ - } - valid_mask &= ~SCR_NET; + /* + * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always + * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64. + * Instead, choose the format based on the mode of EL3. + */ + if (arm_el_is_aa64(env, 3)) { + value |= SCR_FW | SCR_AW; /* RES1 */ + valid_mask &= ~SCR_NET; /* RES0 */ if (cpu_isar_feature(aa64_ras, cpu)) { valid_mask |= SCR_TERR; |