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authorRichard Henderson <richard.henderson@linaro.org>2024-10-07 18:54:26 -0700
committerRichard Henderson <richard.henderson@linaro.org>2024-10-13 11:27:06 -0700
commit1ba3cb88775fd7a9defae36855a99a2c64942905 (patch)
treee032969a66a382fd291cd4923c9efafc4c0323bc /target/arm/internals.h
parent64bda5106c56faa19a31e091aef3a08249cc4ad0 (diff)
downloadfocaccia-qemu-1ba3cb88775fd7a9defae36855a99a2c64942905.tar.gz
focaccia-qemu-1ba3cb88775fd7a9defae36855a99a2c64942905.zip
target/arm: Implement TCGCPUOps.tlb_fill_align
Fill in the tlb_fill_align hook.  Handle alignment not due to
memory type, since that's no longer handled by generic code.
Pass memop to get_phys_addr.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
-rw-r--r--target/arm/internals.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h
index a6088d551c..299a96a81a 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -816,9 +816,9 @@ void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
 void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr,
                            MMUAccessType access_type, uintptr_t ra);
 #else
-bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                      MMUAccessType access_type, int mmu_idx,
-                      bool probe, uintptr_t retaddr);
+bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,
+                            MMUAccessType access_type, int mmu_idx,
+                            MemOp memop, int size, bool probe, uintptr_t ra);
 #endif
 
 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)