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authorFabiano Rosas <farosas@suse.de>2023-04-26 15:00:05 -0300
committerPeter Maydell <peter.maydell@linaro.org>2023-05-02 10:21:32 +0100
commit39920a04952b67fb1fce8fc3519ac18b7a95f3f3 (patch)
tree7e918d8d65075eaf4ca2f527ccd2ec286077cc58 /target/arm/internals.h
parentfcab465e264e18ca74f0513b8f5b682c3362ed7f (diff)
downloadfocaccia-qemu-39920a04952b67fb1fce8fc3519ac18b7a95f3f3.tar.gz
focaccia-qemu-39920a04952b67fb1fce8fc3519ac18b7a95f3f3.zip
target/arm: Move 64-bit TCG CPUs into tcg/
Move the 64-bit CPUs that are TCG-only:
- cortex-a35
- cortex-a55
- cortex-a72
- cortex-a76
- a64fx
- neoverse-n1

Keep the CPUs that can be used with KVM:
- cortex-a57
- cortex-a53
- max
- host

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230426180013.14814-6-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
-rw-r--r--target/arm/internals.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h
index b73c540e7e..0df8f3b8bc 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1361,6 +1361,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
+void aarch64_max_tcg_initfn(Object *obj);
+void aarch64_add_pauth_properties(Object *obj);
+void aarch64_add_sve_properties(Object *obj);
+void aarch64_add_sme_properties(Object *obj);
 #endif
 
 /* Read the CONTROL register as the MRS instruction would. */