summary refs log tree commit diff stats
path: root/target/arm/internals.h
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2021-07-23 12:22:54 -1000
committerRichard Henderson <richard.henderson@linaro.org>2021-11-02 07:00:52 -0400
commit39a099ca25670b9fed838a09887fe8a1fdd803d3 (patch)
tree9a19867b4dacfbe6a11662bf75557dd72d18af7f /target/arm/internals.h
parente7424abc201ea06ff91a15fd86a533a22cd8dff4 (diff)
downloadfocaccia-qemu-39a099ca25670b9fed838a09887fe8a1fdd803d3.tar.gz
focaccia-qemu-39a099ca25670b9fed838a09887fe8a1fdd803d3.zip
target/arm: Implement arm_cpu_record_sigbus
Because of the complexity of setting ESR, re-use the existing
arm_cpu_do_unaligned_access function.  This means we have to
handle the exception ourselves in cpu_loop, transforming it
to the appropriate signal.

Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
-rw-r--r--target/arm/internals.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 5a7aaf0f51..89f7610ebc 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -548,6 +548,8 @@ static inline bool arm_extabort_type(MemTxResult result)
 void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
                             MMUAccessType access_type,
                             bool maperr, uintptr_t ra);
+void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr,
+                           MMUAccessType access_type, uintptr_t ra);
 #else
 bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       MMUAccessType access_type, int mmu_idx,