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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-14 18:54:09 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-14 18:54:09 +0100 |
| commit | d28e29a92585e94264628b1b27262fe2d7573f51 (patch) | |
| tree | e956f9c4bd71330f186a36847460999882a6c651 /target/arm/internals.h | |
| parent | 3dabde1128b671f36ac6cb36b97b273139964420 (diff) | |
| parent | ce3bc112cdb1d462e2d52eaa17a7314e7f3af504 (diff) | |
| download | focaccia-qemu-d28e29a92585e94264628b1b27262fe2d7573f51.tar.gz focaccia-qemu-d28e29a92585e94264628b1b27262fe2d7573f51.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170914' into staging
target-arm queue: * v7M: various code cleanups * v7M: set correct BFSR bits on bus fault * v7M: clear exclusive monitor on reset and exception entry/exit * v7M: don't apply priority mask to negative priorities * zcu102: support 'secure' and 'virtualization' machine properties * aarch64: fix ERET single stepping * gpex: implement PCI INTx routing * mps2-an511: fix UART overflow interrupt line wiring # gpg: Signature made Thu 14 Sep 2017 18:50:48 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170914: mps2-an511: Fix wiring of UART overflow interrupt lines hw/pci-host/gpex: Implement PCI INTx routing hw/arm/virt: Set INTx/gsi mapping hw/pci-host/gpex: Set INTx index/gsi mapping target/arm: Avoid an extra temporary for store_exclusive AArch64: Fix single stepping of ERET instruction xlnx-zcu102: Mark the EP108 machine as deprecated xlnx-zcu102: Add a machine level virtualization property xlnx-zcu102: Add a machine level secure property xlnx-zcu102: Manually create the machines xlnx-ep108: Rename to ZCU102 target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit() target/arm: Add and use defines for EXCRET constants target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit() nvic: Don't apply group priority mask to negative priorities target/arm: Get PRECISERR and IBUSERR the right way round target/arm: Clear exclusive monitor on v7M reset, exception entry/exit target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
| -rw-r--r-- | target/arm/internals.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h index 5d7f24c95c..18be3702f2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -61,6 +61,16 @@ FIELD(V7M_CONTROL, NPRIV, 0, 1) FIELD(V7M_CONTROL, SPSEL, 1, 1) FIELD(V7M_CONTROL, FPCA, 2, 1) +/* Bit definitions for v7M exception return payload */ +FIELD(V7M_EXCRET, ES, 0, 1) +FIELD(V7M_EXCRET, RES0, 1, 1) +FIELD(V7M_EXCRET, SPSEL, 2, 1) +FIELD(V7M_EXCRET, MODE, 3, 1) +FIELD(V7M_EXCRET, FTYPE, 4, 1) +FIELD(V7M_EXCRET, DCRS, 5, 1) +FIELD(V7M_EXCRET, S, 6, 1) +FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ + /* * For AArch64, map a given EL to an index in the banked_spsr array. * Note that this mapping and the AArch32 mapping defined in bank_number() @@ -444,6 +454,16 @@ void arm_handle_psci_call(ARMCPU *cpu); #endif /** + * arm_clear_exclusive: clear the exclusive monitor + * @env: CPU env + * Clear the CPU's exclusive monitor, like the guest CLREX instruction. + */ +static inline void arm_clear_exclusive(CPUARMState *env) +{ + env->exclusive_addr = -1; +} + +/** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @s2addr: Address that caused a fault at stage 2 * @stage2: True if we faulted at stage 2 |