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| author | Gustavo Romero <gustavo.romero@linaro.org> | 2025-08-26 11:21:28 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-08-30 16:37:22 +0100 |
| commit | 6e6d5fb4b928f09b46d0fa99830d75cddb22f73b (patch) | |
| tree | 71c13a42cb6327048ac34891ca5652ff99209717 /target/arm/tcg/cpu64.c | |
| parent | 8a60ffe9a8f46ed514656eb4a40d1386c439daf8 (diff) | |
| download | focaccia-qemu-6e6d5fb4b928f09b46d0fa99830d75cddb22f73b.tar.gz focaccia-qemu-6e6d5fb4b928f09b46d0fa99830d75cddb22f73b.zip | |
target/arm: Implement FEAT_TCR2 and enable with -cpu max
Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers. These registers are extensions of the TCR_ELx registers and provide top-level control of the EL10 and EL20 translation regimes. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250727074202.83141-5-richard.henderson@linaro.org Message-ID: <20250711140828.1714666-5-gustavo.romero@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/tcg/cpu64.c')
| -rw-r--r-- | target/arm/tcg/cpu64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index f4efff03a5..4eb51420ef 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1248,6 +1248,7 @@ void aarch64_max_tcg_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR2, t); t = GET_IDREG(isar, ID_AA64MMFR3); + t = FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ t = FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ SET_IDREG(isar, ID_AA64MMFR3, t); |