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| author | Marc-André Lureau <marcandre.lureau@redhat.com> | 2022-03-23 19:57:18 +0400 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-04-06 10:50:37 +0200 |
| commit | ee3eb3a7ce7242735e6fd64cad53482e3df5a5ec (patch) | |
| tree | e44d5190b97904e26b30b974002dcbfd6fbe5c80 /target/arm | |
| parent | e03b56863d2bca3e649e81531c1b0299524481ae (diff) | |
| download | focaccia-qemu-ee3eb3a7ce7242735e6fd64cad53482e3df5a5ec.tar.gz focaccia-qemu-ee3eb3a7ce7242735e6fd64cad53482e3df5a5ec.zip | |
Replace TARGET_WORDS_BIGENDIAN
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1, and thus should always be defined to prevent misuse. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Suggested-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-8-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/cpu.c | 2 | ||||
| -rw-r--r-- | target/arm/cpu.h | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5d4ca7a227..0980d33901 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -812,7 +812,7 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) sctlr_b = arm_sctlr_b(env); if (bswap_code(sctlr_b)) { -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN info->endian = BFD_ENDIAN_LITTLE; #else info->endian = BFD_ENDIAN_BIG; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 816aa0394e..ccf635ac5c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3549,12 +3549,12 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) static inline bool bswap_code(bool sctlr_b) { #ifdef CONFIG_USER_ONLY - /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. - * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 + /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. + * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 * would also end up as a mixed-endian mode with BE code, LE data. */ return -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN 1 ^ #endif sctlr_b; @@ -3570,7 +3570,7 @@ static inline bool bswap_code(bool sctlr_b) static inline bool arm_cpu_bswap_data(CPUARMState *env) { return -#ifdef TARGET_WORDS_BIGENDIAN +#if TARGET_BIG_ENDIAN 1 ^ #endif arm_cpu_data_is_big_endian(env); |