diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2025-03-23 10:16:23 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-04-22 14:07:12 -0700 |
| commit | 6b661b7ed7cd02c54a78426d5eb7dd8543b030ed (patch) | |
| tree | 8f7b1ccbefa13965cbc3b8c41fa3f78b454769d2 /target/avr/translate.c | |
| parent | 1da8f3a3c53b604edfe0d55e475102640490549e (diff) | |
| download | focaccia-qemu-6b661b7ed7cd02c54a78426d5eb7dd8543b030ed.tar.gz focaccia-qemu-6b661b7ed7cd02c54a78426d5eb7dd8543b030ed.zip | |
target/avr: Improve decode of LDS, STS
The comment about not being able to define a field with
zero bits is out of date since 94597b6146f3
("decodetree: Allow !function with no input bits").
This fixes the missing load of imm in the disassembler.
Cc: qemu-stable@nongnu.org
Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling via option '-d in_asm'")
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/avr/translate.c')
| -rw-r--r-- | target/avr/translate.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target/avr/translate.c b/target/avr/translate.c index 4ab71d8138..e7f8ced9b3 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1578,7 +1578,6 @@ static bool trans_LDS(DisasContext *ctx, arg_LDS *a) TCGv Rd = cpu_r[a->rd]; TCGv addr = tcg_temp_new_i32(); TCGv H = cpu_rampD; - a->imm = next_word(ctx); tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ tcg_gen_shli_tl(addr, addr, 16); @@ -1783,7 +1782,6 @@ static bool trans_STS(DisasContext *ctx, arg_STS *a) TCGv Rd = cpu_r[a->rd]; TCGv addr = tcg_temp_new_i32(); TCGv H = cpu_rampD; - a->imm = next_word(ctx); tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ tcg_gen_shli_tl(addr, addr, 16); |