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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-05-18 20:44:34 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-05-18 20:44:34 -0700 |
| commit | 449d6d9eb44772e69f11d002e3c1e2be8a91c350 (patch) | |
| tree | 124ca1db8453cbdb7a9c6ab83c84785ed1097405 /target/hexagon/gen_idef_parser_funcs.py | |
| parent | 146f515110e86aefe3bc2e8eb581ab724614060f (diff) | |
| parent | 9073bfd725440da0af44f1ee1e3bcf72e9de39b6 (diff) | |
| download | focaccia-qemu-449d6d9eb44772e69f11d002e3c1e2be8a91c350.tar.gz focaccia-qemu-449d6d9eb44772e69f11d002e3c1e2be8a91c350.zip | |
Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into staging
Hexagon update # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmRmgQgACgkQewJE+xLe # RCJLtAf8C/0kQRa4mjnbsztXuFyca53UxAv3BSBEDla4ZcMfFBoVJsGB3OP7IPXd # KBQpkLyJAVye9idex5xqdp9nIfoGKDTsc6YtCfGujZ17cDpzLRDpHdUTex8PcZYK # wpfM3hoVJsYRBMsojZ4OaxatjFQ+FWzrIH6FcgH086Q8TH4w9dZLNEJzHC4lOj0s # 7qOuw2tgm+vOVlzsk/fv6/YD/BTeZTON3jgTPvAnvdRLb/482UpM9JkJ8E4rbte3 # Ss5PUK8QTQHU0yamspGy/PfsYxiptM+jIWGd836fAGzwF12Ug27mSc1enndRtQVW # pQTdnOnWuuRzOwEpd7x3xh9upACm4g== # =1CyJ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 18 May 2023 12:48:24 PM PDT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20230518-1' of https://github.com/quic/qemu: (44 commits) Hexagon (linux-user/hexagon): handle breakpoints Hexagon (gdbstub): add HVX support Hexagon (gdbstub): fix p3:0 read and write via stub Hexagon: add core gdbstub xml data for LLDB gdbstub: add test for untimely stop-reply packets gdbstub: only send stop-reply packets when allowed to Remove test_vshuff from hvx_misc tests Hexagon (decode): look for pkts with multiple insns at the same slot Hexagon (iclass): update J4_hintjumpr slot constraints Hexagon: append eflags to unknown cpu model string Hexagon: list available CPUs with `-cpu help` Hexagon (target/hexagon/*.py): raise exception on reg parsing error target/hexagon: fix = vs. == mishap Hexagon (target/hexagon) Additional instructions handled by idef-parser Hexagon (target/hexagon) Move items to DisasContext Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext Hexagon (target/hexagon) Move pred_written to DisasContext Hexagon (target/hexagon) Move new_pred_value to DisasContext Hexagon (target/hexagon) Move new_value to DisasContext Hexagon (target/hexagon) Make special new_value for USR ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hexagon/gen_idef_parser_funcs.py')
| -rw-r--r-- | target/hexagon/gen_idef_parser_funcs.py | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target/hexagon/gen_idef_parser_funcs.py index afe68bdb6f..29160fcb1d 100644 --- a/target/hexagon/gen_idef_parser_funcs.py +++ b/target/hexagon/gen_idef_parser_funcs.py @@ -103,12 +103,29 @@ def main(): continue if tag.startswith("V6_"): continue - if tag.startswith("F"): + if ( tag.startswith("F") and + tag not in { + "F2_sfimm_p", + "F2_sfimm_n", + "F2_dfimm_p", + "F2_dfimm_n", + "F2_dfmpyll", + "F2_dfmpylh" + }): continue if tag.endswith("_locked"): continue if "A_COF" in hex_common.attribdict[tag]: continue + if ( tag.startswith('R6_release_') ): + continue + ## Skip instructions that are incompatible with short-circuit + ## packet register writes + if ( tag == 'S2_insert' or + tag == 'S2_insert_rp' or + tag == 'S2_asr_r_svw_trun' or + tag == 'A2_swiz' ): + continue regs = tagregs[tag] imms = tagimms[tag] @@ -130,7 +147,7 @@ def main(): elif is_single_new: arguments.append(f"{prefix}{regtype}{regid}N") else: - print("Bad register parse: ", regtype, regid, toss, numregs) + hex_common.bad_register(regtype, regid, toss, numregs) for immlett, bits, immshift in imms: arguments.append(hex_common.imm_name(immlett)) |