Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into staging

Hexagon update

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* tag 'pull-hex-20230518-1' of https://github.com/quic/qemu: (44 commits)
  Hexagon (linux-user/hexagon): handle breakpoints
  Hexagon (gdbstub): add HVX support
  Hexagon (gdbstub): fix p3:0 read and write via stub
  Hexagon: add core gdbstub xml data for LLDB
  gdbstub: add test for untimely stop-reply packets
  gdbstub: only send stop-reply packets when allowed to
  Remove test_vshuff from hvx_misc tests
  Hexagon (decode): look for pkts with multiple insns at the same slot
  Hexagon (iclass): update J4_hintjumpr slot constraints
  Hexagon: append eflags to unknown cpu model string
  Hexagon: list available CPUs with `-cpu help`
  Hexagon (target/hexagon/*.py): raise exception on reg parsing error
  target/hexagon: fix = vs. == mishap
  Hexagon (target/hexagon) Additional instructions handled by idef-parser
  Hexagon (target/hexagon) Move items to DisasContext
  Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext
  Hexagon (target/hexagon) Move pred_written to DisasContext
  Hexagon (target/hexagon) Move new_pred_value to DisasContext
  Hexagon (target/hexagon) Move new_value to DisasContext
  Hexagon (target/hexagon) Make special new_value for USR
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

1 files changed, 16 insertions, 3 deletions

diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 40f28ca933..f3aac55db0 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -30,6 +30,9 @@ tags = []  # list of all tags
 overrides = {}  # tags with helper overrides
 idef_parser_enabled = {}  # tags enabled for idef-parser
 
+def bad_register(*args):
+    args_str = ", ".join(map(str, args))
+    raise Exception(f"Bad register parse: {args_str}")
 
 # We should do this as a hash for performance,
 # but to keep order let's keep it as a list.
@@ -97,6 +100,12 @@ def calculate_attribs():
     add_qemu_macro_attrib("fSET_LPCFG", "A_IMPLICIT_WRITES_USR")
     add_qemu_macro_attrib("fLOAD", "A_SCALAR_LOAD")
     add_qemu_macro_attrib("fSTORE", "A_SCALAR_STORE")
+    add_qemu_macro_attrib('fLSBNEW0', 'A_IMPLICIT_READS_P0')
+    add_qemu_macro_attrib('fLSBNEW0NOT', 'A_IMPLICIT_READS_P0')
+    add_qemu_macro_attrib('fREAD_P0', 'A_IMPLICIT_READS_P0')
+    add_qemu_macro_attrib('fLSBNEW1', 'A_IMPLICIT_READS_P1')
+    add_qemu_macro_attrib('fLSBNEW1NOT', 'A_IMPLICIT_READS_P1')
+    add_qemu_macro_attrib('fREAD_P3', 'A_IMPLICIT_READS_P3')
 
     # Recurse down macros, find attributes from sub-macros
     macroValues = list(macros.values())
@@ -241,9 +250,10 @@ def is_new_val(regtype, regid, tag):
 
 def need_slot(tag):
     if (
-        ("A_CONDEXEC" in attribdict[tag] and "A_JUMP" not in attribdict[tag])
-        or "A_STORE" in attribdict[tag]
-        or "A_LOAD" in attribdict[tag]
+        "A_CVI_SCATTER" not in attribdict[tag]
+        and "A_CVI_GATHER" not in attribdict[tag]
+        and ("A_STORE" in attribdict[tag]
+             or "A_LOAD" in attribdict[tag])
     ):
         return 1
     else:
@@ -270,6 +280,9 @@ def need_pkt_has_multi_cof(tag):
     return "A_COF" in attribdict[tag]
 
 
+def need_pkt_need_commit(tag):
+    return 'A_IMPLICIT_WRITES_USR' in attribdict[tag]
+
 def need_condexec_reg(tag, regs):
     if "A_CONDEXEC" in attribdict[tag]:
         for regtype, regid, toss, numregs in regs: