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| author | Yang Weijiang <weijiang.yang@intel.com> | 2022-02-15 14:52:55 -0500 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-05-14 12:32:41 +0200 |
| commit | 10f0abcb3b8a74a4db1412e844b9192dc9768e94 (patch) | |
| tree | 5a33ee22e30657f52c25078ff5d6421fd35aec12 /target/i386/cpu.c | |
| parent | 301e90675c3fed6cdc48682021a1ab42bc0e0d76 (diff) | |
| download | focaccia-qemu-10f0abcb3b8a74a4db1412e844b9192dc9768e94.tar.gz focaccia-qemu-10f0abcb3b8a74a4db1412e844b9192dc9768e94.zip | |
target/i386: Add XSAVES support for Arch LBR
Define Arch LBR bit in XSS and save/restore structure for XSAVE area size calculation. Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> Message-Id: <20220215195258.29149-6-weijiang.yang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.c')
| -rw-r--r-- | target/i386/cpu.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 643536d05d..1816c37852 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1411,7 +1411,7 @@ static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { #undef REGISTER /* CPUID feature bits available in XSS */ -#define CPUID_XSTATE_XSS_MASK (0) +#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { [XSTATE_FP_BIT] = { @@ -1445,6 +1445,10 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { [XSTATE_PKRU_BIT] = { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, .size = sizeof(XSavePKRU) }, + [XSTATE_ARCH_LBR_BIT] = { + .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, + .offset = 0 /*supervisor mode component, offset = 0 */, + .size = sizeof(XSavesArchLBR) }, [XSTATE_XTILE_CFG_BIT] = { .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, .size = sizeof(XSaveXTILECFG), |