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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-03-22 09:37:38 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-03-22 09:37:38 +0000 |
| commit | d97a39d903fe33c45be83ac6943a2f82a3649a11 (patch) | |
| tree | 8ea0570b32d20bea33ea6977f44b838613f5f0f3 /target/i386/cpu.c | |
| parent | c692931cda9dc6cbc16b89d5094a725a10dbb641 (diff) | |
| parent | 21ee4787e53367590f284915bf4c30c684e65bdf (diff) | |
| download | focaccia-qemu-d97a39d903fe33c45be83ac6943a2f82a3649a11.tar.gz focaccia-qemu-d97a39d903fe33c45be83ac6943a2f82a3649a11.zip | |
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging
x86 queue for -rc1 A few fixes that missed -rc0: * CPU model documentation updates (Daniel P. Berrangé) * Fix bogus OSPKE warnings (Eduardo Habkost) * Work around KVM bugs when handing arch_capabilities (Eduardo Habkost) # gpg: Signature made Thu 21 Mar 2019 19:32:02 GMT # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: docs: add note about stibp CPU feature for spectre v2 docs: clarify that spec-ctrl is only needed for Spectre v2 i386: Disable OSPKE on CPU model definitions i386: Make arch_capabilities migratable i386: kvm: Disable arch_capabilities if MSR can't be set Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/i386/cpu.c')
| -rw-r--r-- | target/i386/cpu.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d90c01a059..d6bb57d210 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1089,7 +1089,6 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .reg = R_EDX, }, .tcg_features = TCG_7_0_EDX_FEATURES, - .unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES, }, [FEAT_8000_0007_EDX] = { .type = CPUID_FEATURE_WORD, @@ -2533,7 +2532,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, .features[FEAT_7_0_ECX] = - CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | + CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_AVX512VNNI, .features[FEAT_7_0_EDX] = CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, @@ -2586,7 +2585,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_SMAP, .features[FEAT_7_0_ECX] = CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | - CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI | + CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI | CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | CPUID_7_0_ECX_AVX512_VPOPCNTDQ, @@ -2644,7 +2643,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, .features[FEAT_7_0_ECX] = CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | - CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI | + CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI | CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, |