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| author | Stefan Hajnoczi <stefanha@redhat.com> | 2025-06-04 11:43:30 -0400 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2025-06-04 11:43:31 -0400 |
| commit | f8a113701dd2d28f3bedb216e59125ddcb77fd05 (patch) | |
| tree | 55ce05f7943dc3bbb1fbb36f28b22f2608b0f831 /target/i386/cpu.h | |
| parent | 09be8a511a2e278b45729d7b065d30c68dd699d0 (diff) | |
| parent | 214518614c1ce7eb7a002452cd43a7597f90d543 (diff) | |
| download | focaccia-qemu-f8a113701dd2d28f3bedb216e59125ddcb77fd05.tar.gz focaccia-qemu-f8a113701dd2d28f3bedb216e59125ddcb77fd05.zip | |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* rust: use native Meson support for clippy and rustdoc * rust: add "bits", a custom bitflags implementation * target/i386: Remove FRED dependency on WRMSRNS * target/i386: Add the immediate form MSR access instruction support * TDX fixes # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmg/XrsUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOPIwf/VXh98Wd+7BJLkNJVFpczSF7YhJ5J # a5BcWLOdVrzEJoqvfc9lkubgpShgzYDYJH99F/FloHddkPvZ1NRB2JXtDB1O3sSC # NGaI4YM8uA/k21pt1jQtDJkk3Az7GNIBIcvi4HR5GjTOvOKGOXLpYErK52lM4GNG # Aa17/Rb9Ug+QzyuS1M+mDPFdY2X6Hore2jXsp3ZH+U8hs+khecHEPsZUZ/Nlr1Z7 # UoiYks4U29wtVJ/BCjNkgXoMJC6uqL/nOP5dLJBgboOodrtwdwpDMIUcyPLrOnjf # ugJx0zYHIVdqpdft72EvLD92bzB8WoUiPsUA/dG45gGmhzuYWDmOqSdaKg== # =l0gm # -----END PGP SIGNATURE----- # gpg: Signature made Tue 03 Jun 2025 16:44:43 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: rust: qemu-api-macros: add from_bits and into_bits to #[derive(TryInto)] rust: pl011: use the bits macro rust: add "bits", a custom bitflags implementation i386/tdvf: Fix build on 32-bit host i386/tdx: Fix build on 32-bit host meson: use config_base_arch for target libraries target/i386: Add the immediate form MSR access instruction support target/i386: Add a new CPU feature word for CPUID.7.1.ECX target/i386: Remove FRED dependency on WRMSRNS rust: use native Meson support for clippy and rustdoc rust: cell: remove support for running doctests with "cargo test --doc" rust: add qemu-api doctests to "meson test" build, dockerfiles: add support for detecting rustdoc rust: use "objects" for Rust executables as well meson: update to version 1.8.1 rust: bindings: allow ptr_offset_with_cast Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1146465c8c..545851cbde 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -668,6 +668,7 @@ typedef enum FeatureWord { FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */ FEAT_XSAVE_XSS_LO, /* CPUID[EAX=0xd,ECX=1].ECX */ FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ + FEAT_7_1_ECX, /* CPUID[EAX=7,ECX=1].ECX */ FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */ @@ -1000,6 +1001,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); /* Linear Address Masking */ #define CPUID_7_1_EAX_LAM (1U << 26) +/* The immediate form of MSR access instructions */ +#define CPUID_7_1_ECX_MSR_IMM (1U << 5) + /* Support for VPDPB[SU,UU,SS]D[,S] */ #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) /* AVX NE CONVERT Instructions */ @@ -1023,6 +1027,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_7_2_EDX_DDPD_U (1U << 3) /* Indicate bit 10 of the IA32_SPEC_CTRL MSR is supported */ #define CPUID_7_2_EDX_BHI_CTRL (1U << 4) + /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */ #define CPUID_7_2_EDX_MCDT_NO (1U << 5) |