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| author | Rui Wang <wangrui@loongson.cn> | 2022-11-04 12:05:17 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2022-11-04 17:10:53 +0800 |
| commit | 2419978cb09e11bc53a07d4de5621424d2a6a86d (patch) | |
| tree | 4eb072b4509af7c1f61b8aa57188c61d42441324 /target/loongarch/cpu.c | |
| parent | b4bda2006f482f778d9dbf86038ff115fe89db92 (diff) | |
| download | focaccia-qemu-2419978cb09e11bc53a07d4de5621424d2a6a86d.tar.gz focaccia-qemu-2419978cb09e11bc53a07d4de5621424d2a6a86d.zip | |
target/loongarch: Fix emulation of float-point disable exception
We need to emulate it to generate a floating point disable exception when CSR.EUEN.FPE is zero. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Rui Wang <wangrui@loongson.cn> Message-Id: <20221104040517.222059-3-wangrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Diffstat (limited to 'target/loongarch/cpu.c')
| -rw-r--r-- | target/loongarch/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 1512664214..46b04cbdad 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -48,6 +48,7 @@ static const char * const excp_names[] = { [EXCCODE_BRK] = "Break", [EXCCODE_INE] = "Instruction Non-Existent", [EXCCODE_IPE] = "Instruction privilege error", + [EXCCODE_FPD] = "Floating Point Disabled", [EXCCODE_FPE] = "Floating Point Exception", [EXCCODE_DBP] = "Debug breakpoint", [EXCCODE_BCE] = "Bound Check Exception", @@ -185,6 +186,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) case EXCCODE_BRK: case EXCCODE_INE: case EXCCODE_IPE: + case EXCCODE_FPD: case EXCCODE_FPE: case EXCCODE_BCE: env->CSR_BADV = env->pc; |