diff options
| author | Bibo Mao <maobibo@loongson.cn> | 2025-07-29 10:44:51 +0800 |
|---|---|---|
| committer | Bibo Mao <maobibo@loongson.cn> | 2025-08-29 10:05:02 +0800 |
| commit | 912f75eaed5f686fe0f312e8ac797be7c1f43b0e (patch) | |
| tree | bd69e58ba98dfc663d97e51846fffa04680c2319 /target/loongarch/cpu_helper.c | |
| parent | a3d4bc4845911d82162f5be782f73e9742a41306 (diff) | |
| download | focaccia-qemu-912f75eaed5f686fe0f312e8ac797be7c1f43b0e.tar.gz focaccia-qemu-912f75eaed5f686fe0f312e8ac797be7c1f43b0e.zip | |
target/loongarch: Add enum type TLBRet definition
There is mixed usage between enum variable TLBRET_xxx and int type, here add enum type TLBRet definition and replace int type variable with enum type TLBRet in some functions. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/loongarch/cpu_helper.c')
| -rw-r--r-- | target/loongarch/cpu_helper.c | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 418122f447..17a0735f5c 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -44,8 +44,9 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, } } -static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *physical, - int *prot, target_ulong address) +static TLBRet loongarch_page_table_walker(CPULoongArchState *env, + hwaddr *physical, + int *prot, target_ulong address) { CPUState *cs = env_cpu(env); target_ulong index, phys; @@ -116,15 +117,15 @@ static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *physical, /* mask other attribute bits */ *physical = base & TARGET_PAGE_MASK; - return 0; + return TLBRET_MATCH; } -static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical, - int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx, - int is_debug) +static TLBRet loongarch_map_address(CPULoongArchState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type, int mmu_idx, + int is_debug) { - int ret; + TLBRet ret; if (tcg_enabled()) { ret = loongarch_get_addr_from_tlb(env, physical, prot, address, @@ -158,9 +159,10 @@ static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va, } } -int get_physical_address(CPULoongArchState *env, hwaddr *physical, - int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx, int is_debug) +TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type, int mmu_idx, + int is_debug) { int user_mode = mmu_idx == MMU_USER_IDX; int kernel_mode = mmu_idx == MMU_KERNEL_IDX; @@ -214,7 +216,7 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int prot; if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(cs, false), 1) != 0) { + cpu_mmu_index(cs, false), 1) != TLBRET_MATCH) { return -1; } return phys_addr; |