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| author | Laurent Vivier <laurent@vivier.eu> | 2018-01-18 20:38:45 +0100 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2018-01-25 16:02:25 +0100 |
| commit | e55886c3340c3a3f1267a3a3d42082008bb255fb (patch) | |
| tree | 31bd715c14a4acccb313d417817faa0ab0799aca /target/m68k/cpu.h | |
| parent | 5fa9f1f28321f7268e68e58cff8c61a2ab817f91 (diff) | |
| download | focaccia-qemu-e55886c3340c3a3f1267a3a3d42082008bb255fb.tar.gz focaccia-qemu-e55886c3340c3a3f1267a3a3d42082008bb255fb.zip | |
target/m68k: add pflush/ptest
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-7-laurent@vivier.eu>
Diffstat (limited to 'target/m68k/cpu.h')
| -rw-r--r-- | target/m68k/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index cc1759bb5d..0739c3f5c8 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -131,6 +131,7 @@ typedef struct CPUM68KState { uint32_t srp; bool fault; uint32_t ttr[4]; + uint32_t mmusr; } mmu; /* Control registers. */ @@ -512,6 +513,8 @@ enum { ACCESS_STORE = 0x02, /* 1 bit to indicate debug access */ ACCESS_DEBUG = 0x04, + /* PTEST instruction */ + ACCESS_PTEST = 0x08, /* Type of instruction that generated the access */ ACCESS_CODE = 0x10, /* Code fetch access */ ACCESS_DATA = 0x20, /* Data load/store access */ |