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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-03-28 12:55:24 -0500 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-03-31 21:32:43 +0200 |
| commit | fca2817fdcb00e65020c2dcfcb0b23b2a20ea3c4 (patch) | |
| tree | 534c1788a5de453e84ff6d1e660e64b20665b756 /target/mips/cpu-param.h | |
| parent | 8001d22b0c67b2fbf8f2cb7b2f44bd7b46b360c1 (diff) | |
| download | focaccia-qemu-fca2817fdcb00e65020c2dcfcb0b23b2a20ea3c4.tar.gz focaccia-qemu-fca2817fdcb00e65020c2dcfcb0b23b2a20ea3c4.zip | |
target/mips: Revert TARGET_PAGE_BITS_VARY
Revert ee3863b9d41 and a08d60bc6c2b. The logic behind changing the system page size because of what the Loongson kernel "prefers" is flawed. In the Loongson-2E manual, section 5.5, it is clear that the cpu supports a 4k page size (along with many others). Similarly for the Loongson-3 series CPUs, the 4k page size is mentioned in the section 7.7 (PageMask Register). Therefore we must continue to support a 4k page size. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250328175526.368121-2-richard.henderson@linaro.org> [PMD: Mention Loongson-3 series CPUs] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'target/mips/cpu-param.h')
| -rw-r--r-- | target/mips/cpu-param.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 11b3ac0ac6..8fcb1b4f5f 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -18,12 +18,7 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif #endif -#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 -#else -#define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 -#endif #define TCG_GUEST_DEFAULT_MO (0) |