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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-10-21 11:33:19 -0300 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-03 05:52:49 -0300 |
| commit | 09968fc96cee3d32e03b26b916bd6195f959c3d7 (patch) | |
| tree | e0c5d459319c6a9528795307e3d6c2c0dc8109fb /target/mips/cpu.h | |
| parent | 74665884a594a12c744eb7405015b2d2e8df4621 (diff) | |
| download | focaccia-qemu-09968fc96cee3d32e03b26b916bd6195f959c3d7.tar.gz focaccia-qemu-09968fc96cee3d32e03b26b916bd6195f959c3d7.zip | |
target/mips: Introduce ase_3d_available() helper
Determine if the MIPS-3D ASE is implemented by checking the state of the 3D bit in the FIR CP1 control register. Remove the then unused ASE_MIPS3D definition. Note, this allows using MIPS-3D on the mips64dspr2 model. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241021145832.34920-1-philmd@linaro.org>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a4a46ebbe9..3dbfbfdb3d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1319,6 +1319,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); +/* Check presence of MIPS-3D ASE */ +static inline bool ase_3d_available(const CPUMIPSState *env) +{ + return env->active_fpu.fcr0 & (1 << FCR0_3D); +} + /* Check presence of MSA implementation */ static inline bool ase_msa_available(CPUMIPSState *env) { |