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authorAleksandar Markovic <amarkovic@wavecomp.com>2019-08-28 18:26:25 +0200
committerAleksandar Markovic <amarkovic@wavecomp.com>2019-08-29 11:50:18 +0200
commit1b142da5f82a8fcdc7783a418592de654d5c6052 (patch)
tree80ee001b778551f2fc2812015fb91944f9f13f0d /target/mips/cpu.h
parent705be570941b38cd1cbebc68f7f671ce7532ecb0 (diff)
downloadfocaccia-qemu-1b142da5f82a8fcdc7783a418592de654d5c6052.tar.gz
focaccia-qemu-1b142da5f82a8fcdc7783a418592de654d5c6052.zip
target/mips: Clean up handling of CP0 register 0
Clean up handling of CP0 register 0.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-2-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'target/mips/cpu.h')
-rw-r--r--target/mips/cpu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 1fd4a180e1..42d0e44e81 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -277,6 +277,9 @@ typedef struct mips_def_t mips_def_t;
 
 /* CP0 Register 00 */
 #define CP0_REG00__INDEX           0
+#define CP0_REG00__MVPCONTROL      1
+#define CP0_REG00__MVPCONF0        2
+#define CP0_REG00__MVPCONF1        3
 #define CP0_REG00__VPCONTROL       4
 /* CP0 Register 01 */
 /* CP0 Register 02 */