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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-01-30 14:18:45 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-01-30 14:18:45 +0000 |
| commit | 204aa60b37c23a89e690d418f49787d274303ca7 (patch) | |
| tree | 902d059da93888c408d17ede0d92a1038cd4ff67 /target/mips/cpu.h | |
| parent | a09a2b5a4d85d4bf2f04b0e503d7dd7905967148 (diff) | |
| parent | 99029be1c2875cd857614397674bbf563ddb6f91 (diff) | |
| download | focaccia-qemu-204aa60b37c23a89e690d418f49787d274303ca7.tar.gz focaccia-qemu-204aa60b37c23a89e690d418f49787d274303ca7.zip | |
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jan-29-2020' into staging
MIPS queue for January 29th, 2020 # gpg: Signature made Wed 29 Jan 2020 18:29:43 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full] # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-jan-29-2020: target/mips: Add implementation of GINVT instruction target/mips: Amend CP0 WatchHi register implementation hw/core/loader: Let load_elf() populate a field with CPU-specific flags target/mips: semihosting: Remove 'uhi_done' label in helper_do_semihosting() disas: Add a field for target-dependant data to disassemble_info target/mips: Rectify documentation on deprecating MIPS r4k machine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index c218ccc4a8..94d01ea798 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -309,7 +309,7 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG04__USERLOCAL 2 #define CP0_REG04__XCONTEXTCONFIG 3 #define CP0_REG04__DBGCONTEXTID 4 -#define CP0_REG00__MMID 5 +#define CP0_REG04__MMID 5 /* CP0 Register 05 */ #define CP0_REG05__PAGEMASK 0 #define CP0_REG05__PAGEGRAIN 1 @@ -961,7 +961,7 @@ struct CPUMIPSState { /* * CP0 Register 19 */ - int32_t CP0_WatchHi[8]; + uint64_t CP0_WatchHi[8]; #define CP0WH_ASID 16 /* * CP0 Register 20 |