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| author | Yongbok Kim <yongbok.kim@mips.com> | 2018-10-09 18:42:46 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-18 20:37:20 +0200 |
| commit | 20b28ebc49945583d7191b57755cfd92433de9ff (patch) | |
| tree | 6b208ad43fab225372cacefb1def8f370b390252 /target/mips/cpu.h | |
| parent | fa75ad1459f4f6abbeb6d375a812dfad61320f58 (diff) | |
| download | focaccia-qemu-20b28ebc49945583d7191b57755cfd92433de9ff.tar.gz focaccia-qemu-20b28ebc49945583d7191b57755cfd92433de9ff.zip | |
target/mips: Add CP0 PWSize register
Add PWSize register (CP0 Register 5, Select 7). The PWSize register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: BDW (37..32) Base Directory index width (MIPS64 only) GDW (29..24) Global Directory index width UDW (23..18) Upper Directory index width MDW (17..12) Middle Directory index width PTW (11..6 ) Page Table index width PTEW ( 5..0 ) Left shift applied to the Page Table index Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 31c9583236..3475b2f323 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -432,6 +432,16 @@ struct CPUMIPSState { #define CP0PF_PTW 6 /* 11..6 */ #define CP0PF_PTEW 0 /* 5..0 */ #endif + target_ulong CP0_PWSize; +#if defined(TARGET_MIPS64) +#define CP0PS_BDW 32 /* 37..32 */ +#endif +#define CP0PS_PS 30 +#define CP0PS_GDW 24 /* 29..24 */ +#define CP0PS_UDW 18 /* 23..18 */ +#define CP0PS_MDW 12 /* 17..12 */ +#define CP0PS_PTW 6 /* 11..6 */ +#define CP0PS_PTEW 0 /* 5..0 */ /* * CP0 Register 6 */ |