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| author | Marcin Nowakowski <marcin.nowakowski@fungible.com> | 2023-02-16 06:17:16 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-03-08 00:37:48 +0100 |
| commit | 36b84f856ed67f5b2ee2e26368f7009f3222ba46 (patch) | |
| tree | 245e3cd89a701498b26445d09fe39b417b27e5c7 /target/mips/cpu.h | |
| parent | 7c00edb9a2e2cb975a60e80dbe1e66287a9d5777 (diff) | |
| download | focaccia-qemu-36b84f856ed67f5b2ee2e26368f7009f3222ba46.tar.gz focaccia-qemu-36b84f856ed67f5b2ee2e26368f7009f3222ba46.zip | |
target/mips: Implement CP0.Config7.WII bit support
Some pre-release 6 cores use CP0.Config7.WII bit to indicate that a disabled interrupt should wake up a sleeping CPU. Enable this bit by default for M14K(c) and P5600. There are potentially other cores that support this feature, but I do not have a complete list. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230216051717.3911212-4-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index caf2b06911..142c55af47 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -980,6 +980,7 @@ typedef struct CPUArchState { #define CP0C6_DATAPREF 0 int32_t CP0_Config7; int64_t CP0_Config7_rw_bitmask; +#define CP0C7_WII 31 #define CP0C7_NAPCGEN 2 #define CP0C7_UNIMUEN 1 #define CP0C7_VFPUCGEN 0 |