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| author | Yongbok Kim <yongbok.kim@mips.com> | 2018-10-09 18:05:51 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-18 20:37:20 +0200 |
| commit | 5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6 (patch) | |
| tree | aec770ca83d1d53eccd57353bf6b5e5eadea272a /target/mips/cpu.h | |
| parent | 49735f76db25bf10f57973d5249f17151b801760 (diff) | |
| download | focaccia-qemu-5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6.tar.gz focaccia-qemu-5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6.zip | |
target/mips: Add CP0 PWBase register
Add PWBase register (CP0 Register 5, Select 5). The PWBase register contains the Page Table Base virtual address. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 953643b037..9cbde99edd 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -416,6 +416,7 @@ struct CPUMIPSState { #define CP0SC2_XR 56 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) + target_ulong CP0_PWBase; /* * CP0 Register 6 */ |