target/mips: Provide R/W access to SAARI and SAAR CP0 registers

Provide R/W access to SAARI and SAAR CP0 registers.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 1c2c6824fd..185702d1e9 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -901,6 +901,7 @@ struct CPUMIPSState {
     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
     uint64_t insn_flags; /* Supported instruction set */
+    int saarp;
 
     /* Fields up to this point are cleared by a CPU reset */
     struct {} end_reset_fields;