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| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-28 18:26:52 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-08-29 12:08:10 +0200 |
| commit | af4bb6da80d3f6c733055bb4e2a1b99a30e81d24 (patch) | |
| tree | e0f4c0d5dc9f15699570f04dfda9bc8d9d5d30fa /target/mips/cpu.h | |
| parent | a30e2f218034f6215757734c8107fd47f5385dfa (diff) | |
| download | focaccia-qemu-af4bb6da80d3f6c733055bb4e2a1b99a30e81d24.tar.gz focaccia-qemu-af4bb6da80d3f6c733055bb4e2a1b99a30e81d24.zip | |
target/mips: Clean up handling of CP0 register 29
Clean up handling of CP0 register 29. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-29-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index de9e850a21..6defbea5b3 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -233,12 +233,12 @@ typedef struct mips_def_t mips_def_t; * * 0 DataLo DataHi ErrorEPC DESAVE * 1 TagLo TagHi - * 2 DataLo1 DataHi KScratch<n> - * 3 TagLo1 TagHi KScratch<n> - * 4 DataLo2 DataHi KScratch<n> - * 5 TagLo2 TagHi KScratch<n> - * 6 DataLo3 DataHi KScratch<n> - * 7 TagLo3 TagHi KScratch<n> + * 2 DataLo1 DataHi1 KScratch<n> + * 3 TagLo1 TagHi1 KScratch<n> + * 4 DataLo2 DataHi2 KScratch<n> + * 5 TagLo2 TagHi2 KScratch<n> + * 6 DataLo3 DataHi3 KScratch<n> + * 7 TagLo3 TagHi3 KScratch<n> * */ #define CP0_REGISTER_00 0 @@ -436,8 +436,14 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG28__TAGLO3 6 #define CP0_REG28__DATALO3 7 /* CP0 Register 29 */ -#define CP0_REG29__IDATAHI 1 -#define CP0_REG29__DDATAHI 3 +#define CP0_REG29__TAGHI 0 +#define CP0_REG29__DATAHI 1 +#define CP0_REG29__TAGHI1 2 +#define CP0_REG29__DATAHI1 3 +#define CP0_REG29__TAGHI2 4 +#define CP0_REG29__DATAHI2 5 +#define CP0_REG29__TAGHI3 6 +#define CP0_REG29__DATAHI3 7 /* CP0 Register 30 */ #define CP0_REG30__ERROREPC 0 /* CP0 Register 31 */ |