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authorAleksandar Markovic <amarkovic@wavecomp.com>2019-08-29 12:03:36 +0200
committerAleksandar Markovic <amarkovic@wavecomp.com>2019-08-29 12:04:01 +0200
commitbe274dc18ee3682bb3a2ba7e5ccd3061b103cbec (patch)
treedbcd709bb9318ed0cb8a41f693f925431d3871ca /target/mips/cpu.h
parente8dcfe825a51c5e963813343ec4112f06a0acf68 (diff)
downloadfocaccia-qemu-be274dc18ee3682bb3a2ba7e5ccd3061b103cbec.tar.gz
focaccia-qemu-be274dc18ee3682bb3a2ba7e5ccd3061b103cbec.zip
target/mips: Clean up handling of CP0 register 19
Clean up handling of CP0 register 19.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-21-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'target/mips/cpu.h')
-rw-r--r--target/mips/cpu.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d6ea1113d7..b4866a51fd 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -395,6 +395,10 @@ typedef struct mips_def_t mips_def_t;
 #define CP0_REG19__WATCHHI1        1
 #define CP0_REG19__WATCHHI2        2
 #define CP0_REG19__WATCHHI3        3
+#define CP0_REG19__WATCHHI4        4
+#define CP0_REG19__WATCHHI5        5
+#define CP0_REG19__WATCHHI6        6
+#define CP0_REG19__WATCHHI7        7
 /* CP0 Register 20 */
 #define CP0_REG20__XCONTEXT        0
 /* CP0 Register 21 */