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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2024-02-09 08:55:48 +0100
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2024-02-15 15:53:12 +0100
commitfa82742621c3d26cde6383b1c0f891d23f01078f (patch)
tree40d9b4f947e986768cc85e12a256fada4d28e0f1 /target/mips/cpu.h
parentee58fddcbbb2374b62065cd97888e4478aa02a95 (diff)
downloadfocaccia-qemu-fa82742621c3d26cde6383b1c0f891d23f01078f.tar.gz
focaccia-qemu-fa82742621c3d26cde6383b1c0f891d23f01078f.zip
target/mips: Remove CPUMIPSState::CP0_SAARI field
Remove the unused CP0_SAARI register.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-10-philmd@linaro.org>
Diffstat (limited to 'target/mips/cpu.h')
-rw-r--r--target/mips/cpu.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 5e97b5b422..7329226d39 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -747,7 +747,6 @@ typedef struct CPUArchState {
  * CP0 Register 9
  */
     int32_t CP0_Count;
-    uint32_t CP0_SAARI;
 #define CP0SAARI_TARGET 0    /*  5..0  */
 #define CP0SAAR_BASE    12   /* 43..12 */
 #define CP0SAAR_SIZE    1    /*  5..1  */