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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-01-16 18:23:02 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-01-16 18:23:02 +0000 |
| commit | a8c611e1133f97c979922f41103f79309339dc27 (patch) | |
| tree | 73d1c11a4e395d2d71a4c6a5b77018986f8613d8 /target/mips/helper.c | |
| parent | 2ccede18bd24fce5db83fef3674563a1f256717b (diff) | |
| parent | d10eb08f5d8389c814b554d01aa2882ac58221bf (diff) | |
| download | focaccia-qemu-a8c611e1133f97c979922f41103f79309339dc27.tar.gz focaccia-qemu-a8c611e1133f97c979922f41103f79309339dc27.zip | |
Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1' into staging
This is the same as the v3 posted except a re-base and a few extra signoffs # gpg: Signature made Fri 13 Jan 2017 14:26:46 GMT # gpg: using RSA key 0xFBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1: cputlb: drop flush_global flag from tlb_flush cpu_common_reset: wrap TCG specific code in tcg_enabled() qom/cpu: move tlb_flush to cpu_common_reset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/mips/helper.c')
| -rw-r--r-- | target/mips/helper.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/mips/helper.c b/target/mips/helper.c index c864b15b97..d2e77958fd 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -223,12 +223,12 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, return ret; } -void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global) +void cpu_mips_tlb_flush(CPUMIPSState *env) { MIPSCPU *cpu = mips_env_get_cpu(env); /* Flush qemu's TLB and discard all shadowed entries. */ - tlb_flush(CPU(cpu), flush_global); + tlb_flush(CPU(cpu)); env->tlb->tlb_in_use = env->tlb->nb_tlb; } @@ -290,7 +290,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) #if defined(TARGET_MIPS64) if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { /* Access to at least one of the 64-bit segments has been disabled */ - cpu_mips_tlb_flush(env, 1); + cpu_mips_tlb_flush(env); } #endif if (env->CP0_Config3 & (1 << CP0C3_MT)) { |