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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-06-16 11:00:28 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-06-16 11:00:28 +0100 |
| commit | f5e34624f28f37ec3c8a93bdee348effee966a78 (patch) | |
| tree | 5b02fee760aa99984ca27531f230eb79f2805cd7 /target/mips/mips-defs.h | |
| parent | 72fc7d7f7907cbae2d3265e117ce8a21f24adc81 (diff) | |
| parent | 250bc43a406f7d46e319abe87c19548d4f027828 (diff) | |
| download | focaccia-qemu-f5e34624f28f37ec3c8a93bdee348effee966a78.tar.gz focaccia-qemu-f5e34624f28f37ec3c8a93bdee348effee966a78.zip | |
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-15-2020' into staging
MIPS + misc queue for June 15th, 2020 # gpg: Signature made Mon 15 Jun 2020 20:05:25 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full] # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-jun-15-2020: translations: Add Swedish language MAINTAINERS: Adjust sh4 maintainership target/mips: msa: Split helpers for MULV.<B|H|W|D> target/mips: msa: Split helpers for SUBV.<B|H|W|D> target/mips: msa: Split helpers for SUBSUU_S.<B|H|W|D> target/mips: msa: Split helpers for SUBSUS_U.<B|H|W|D> target/mips: msa: Split helpers for SUBS_U.<B|H|W|D> target/mips: msa: Split helpers for SUBS_S.<B|H|W|D> target/mips: msa: Split helpers for DOTP_U.<H|W|D> target/mips: msa: Split helpers for DOTP_S.<H|W|D> target/mips: msa: Split helpers for DPSUB_U.<H|W|D> target/mips: msa: Split helpers for DPSUB_S.<H|W|D> target/mips: msa: Split helpers for DPADD_U.<H|W|D> target/mips: msa: Split helpers for DPADD_S.<H|W|D> target/mips: msa: Split helpers for MSUBV.<B|H|W|D> target/mips: msa: Split helpers for MADDV.<B|H|W|D> target/mips: Add comments for vendor-specific ASEs target/mips: Legalize Loongson insn flags Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/mips/mips-defs.h')
| -rw-r--r-- | target/mips/mips-defs.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 0c129106c8..ed6a7a9e54 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -57,9 +57,13 @@ /* * bits 52-63: vendor-specific ASEs */ +/* MultiMedia Instructions defined by R5900 */ #define ASE_MMI 0x0010000000000000ULL +/* MIPS eXtension/enhanced Unit defined by Ingenic */ #define ASE_MXU 0x0020000000000000ULL +/* Loongson MultiMedia Instructions */ #define ASE_LMMI 0x0040000000000000ULL +/* Loongson EXTensions */ #define ASE_LEXT 0x0080000000000000ULL /* MIPS CPU defines. */ @@ -70,7 +74,7 @@ #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) #define CPU_R5900 (CPU_MIPS3 | INSN_R5900) #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) -#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) +#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) @@ -97,7 +101,7 @@ /* Wave Computing: "nanoMIPS" */ #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) -#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A) +#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT) /* * Strictly follow the architecture standard: |