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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-01-16 18:23:02 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-01-16 18:23:02 +0000 |
| commit | a8c611e1133f97c979922f41103f79309339dc27 (patch) | |
| tree | 73d1c11a4e395d2d71a4c6a5b77018986f8613d8 /target/mips/op_helper.c | |
| parent | 2ccede18bd24fce5db83fef3674563a1f256717b (diff) | |
| parent | d10eb08f5d8389c814b554d01aa2882ac58221bf (diff) | |
| download | focaccia-qemu-a8c611e1133f97c979922f41103f79309339dc27.tar.gz focaccia-qemu-a8c611e1133f97c979922f41103f79309339dc27.zip | |
Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1' into staging
This is the same as the v3 posted except a re-base and a few extra signoffs # gpg: Signature made Fri 13 Jan 2017 14:26:46 GMT # gpg: using RSA key 0xFBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1: cputlb: drop flush_global flag from tlb_flush cpu_common_reset: wrap TCG specific code in tcg_enabled() qom/cpu: move tlb_flush to cpu_common_reset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/mips/op_helper.c')
| -rw-r--r-- | target/mips/op_helper.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 11d781fc91..b683fcb025 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1409,7 +1409,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) /* If the ASID changes, flush qemu's TLB. */ if ((old & env->CP0_EntryHi_ASID_mask) != (val & env->CP0_EntryHi_ASID_mask)) { - cpu_mips_tlb_flush(env, 1); + cpu_mips_tlb_flush(env); } } @@ -1999,7 +1999,7 @@ void r4k_helper_tlbinv(CPUMIPSState *env) tlb->EHINV = 1; } } - cpu_mips_tlb_flush(env, 1); + cpu_mips_tlb_flush(env); } void r4k_helper_tlbinvf(CPUMIPSState *env) @@ -2009,7 +2009,7 @@ void r4k_helper_tlbinvf(CPUMIPSState *env) for (idx = 0; idx < env->tlb->nb_tlb; idx++) { env->tlb->mmu.r4k.tlb[idx].EHINV = 1; } - cpu_mips_tlb_flush(env, 1); + cpu_mips_tlb_flush(env); } void r4k_helper_tlbwi(CPUMIPSState *env) @@ -2123,7 +2123,7 @@ void r4k_helper_tlbr(CPUMIPSState *env) /* If this will change the current ASID, flush qemu's TLB. */ if (ASID != tlb->ASID) - cpu_mips_tlb_flush (env, 1); + cpu_mips_tlb_flush(env); r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |