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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-09-11 18:54:24 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-09-14 12:00:21 -0700 |
| commit | 6eb66e086a5b03ed197ad8db8b637ab304bbc4d9 (patch) | |
| tree | 5ed6a3021cd08706c8bf35a9007f0c2deecc4225 /target/mips/tcg/exception.c | |
| parent | eb3ef3136eb2a56026d7f1516082e14a0c98f152 (diff) | |
| download | focaccia-qemu-6eb66e086a5b03ed197ad8db8b637ab304bbc4d9.tar.gz focaccia-qemu-6eb66e086a5b03ed197ad8db8b637ab304bbc4d9.zip | |
target/mips: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210911165434.531552-15-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips/tcg/exception.c')
| -rw-r--r-- | target/mips/tcg/exception.c | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 4fb8b00711..7b3026b105 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -86,24 +86,6 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) env->hflags |= tb->flags & MIPS_HFLAG_BMASK; } -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index = EXCP_EXT_INTERRUPT; - env->error_code = 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - static const char * const excp_names[EXCP_LAST + 1] = { [EXCP_RESET] = "reset", [EXCP_SRESET] = "soft reset", |