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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-03-21 19:01:52 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-04-23 15:07:32 -0700 |
| commit | 04583ce7e032ee8e0a12756b69dc67ad7b399997 (patch) | |
| tree | 8ce353436dbc2967023b28a8eb2d93a62c2ef01e /target/openrisc/cpu.c | |
| parent | adb86e48ad3db9031a5963e03a8be2e2798bf9d1 (diff) | |
| download | focaccia-qemu-04583ce7e032ee8e0a12756b69dc67ad7b399997.tar.gz focaccia-qemu-04583ce7e032ee8e0a12756b69dc67ad7b399997.zip | |
tcg: Define guest_default_memory_order in TCGCPUOps
Add the TCGCPUOps::guest_default_memory_order field and have each target initialize it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/cpu.c')
| -rw-r--r-- | target/openrisc/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index dc55594a7d..e62c698a40 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -243,6 +243,8 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps openrisc_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = openrisc_translate_init, .translate_code = openrisc_translate_code, .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, |