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| author | Stefan Hajnoczi <stefanha@redhat.com> | 2017-05-05 16:21:00 +0100 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2017-05-05 16:21:16 +0100 |
| commit | 317134bb54bbaf13548c35d92cb00c650a18e32f (patch) | |
| tree | 0b9f925b0bc5b30fa7bd0fc338462c147521c193 /target/openrisc/cpu.c | |
| parent | 4f3652b3aa5f77582c94ac434e960db242430eac (diff) | |
| parent | f4d1414a9385e3375d9107b29eeb75d27daf2147 (diff) | |
| download | focaccia-qemu-317134bb54bbaf13548c35d92cb00c650a18e32f.tar.gz focaccia-qemu-317134bb54bbaf13548c35d92cb00c650a18e32f.zip | |
Merge remote-tracking branch 'shorne/tags/pull-or-20170504' into staging
Openrisc Features and Fixes for qemu 2.10 # gpg: Signature made Thu 04 May 2017 01:41:45 AM BST # gpg: using RSA key 0xC3B31C2D5E6627E4 # gpg: Good signature from "Stafford Horne <shorne@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4 * shorne/tags/pull-or-20170504: target/openrisc: Support non-busy idle state using PMR SPR target/openrisc: Remove duplicate features property target/openrisc: Implement full vmstate serialization migration: Add VMSTATE_STRUCT_2DARRAY() target/openrisc: implement shadow registers migration: Add VMSTATE_UINTTL_2DARRAY() target/openrisc: add numcores and coreid support target/openrisc: Fixes for memory debugging target/openrisc: Implement EPH bit target/openrisc: Implement EVBAR register MAINTAINERS: Add myself as openrisc maintainer Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'target/openrisc/cpu.c')
| -rw-r--r-- | target/openrisc/cpu.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 7fd2b9a216..1d6330cbcc 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -51,8 +51,8 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.lock_addr = -1; s->exception_index = -1; - cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; - cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; + cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | + UPR_PMP; cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); @@ -65,12 +65,6 @@ static void openrisc_cpu_reset(CPUState *s) #endif } -static inline void set_feature(OpenRISCCPU *cpu, int feature) -{ - cpu->feature |= feature; - cpu->env.cpucfgr = cpu->feature; -} - static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -132,15 +126,15 @@ static void or1200_initfn(Object *obj) { OpenRISCCPU *cpu = OPENRISC_CPU(obj); - set_feature(cpu, OPENRISC_FEATURE_OB32S); - set_feature(cpu, OPENRISC_FEATURE_OF32S); + cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | + CPUCFGR_EVBARP; } static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu = OPENRISC_CPU(obj); - set_feature(cpu, OPENRISC_FEATURE_OB32S); + cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; } typedef struct OpenRISCCPUInfo { |