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authorGavin Shan <gshan@redhat.com>2023-11-15 09:56:13 +1000
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2024-01-05 16:20:14 +0100
commit72b381f1339e52a9fc672c39b2611dc1a79899ca (patch)
treed9c5cbebed89c665ae506f3cb1baefe65aa96de1 /target/openrisc/cpu.h
parent31c51470101f43782b6ed4f948b427748777d4db (diff)
downloadfocaccia-qemu-72b381f1339e52a9fc672c39b2611dc1a79899ca.tar.gz
focaccia-qemu-72b381f1339e52a9fc672c39b2611dc1a79899ca.zip
target/openrisc: Use generic cpu_list()
Before it's applied:

[gshan@gshan q]$ ./build/qemu-or1k -cpu ?
Available CPUs:
  or1200
  any

After it's applied:

[gshan@gshan q]$ ./build/qemu-or1k -cpu ?
Available CPUs:
  any
  or1200

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231114235628.534334-17-gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'target/openrisc/cpu.h')
-rw-r--r--target/openrisc/cpu.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index dedeb89f8e..b454014ddd 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -299,15 +299,12 @@ struct ArchCPU {
     CPUOpenRISCState env;
 };
 
-void cpu_openrisc_list(void);
 void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 void openrisc_translate_init(void);
 int print_insn_or1k(bfd_vma addr, disassemble_info *info);
 
-#define cpu_list cpu_openrisc_list
-
 #ifndef CONFIG_USER_ONLY
 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);