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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-08-25 15:23:42 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:51:19 -0700 |
| commit | 8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2 (patch) | |
| tree | 91f063efef1666667185b148b2a33259783f37d8 /target/openrisc/cpu.h | |
| parent | c7efab4fc1fe5092136305a2cae67fca03f4f9c5 (diff) | |
| download | focaccia-qemu-8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2.tar.gz focaccia-qemu-8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2.zip | |
target/openrisc: Add VR2 and AVR special processor registers
Update the CPUCFG bits to arch v1.3. Include support for AVRP for cpu "any". Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/cpu.h')
| -rw-r--r-- | target/openrisc/cpu.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 18d7445e74..71c5959828 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -96,11 +96,12 @@ enum { CPUCFGR_OF32S = (1 << 7), CPUCFGR_OF64S = (1 << 8), CPUCFGR_OV64S = (1 << 9), - /* CPUCFGR_ND = (1 << 10), */ - /* CPUCFGR_AVRP = (1 << 11), */ + CPUCFGR_ND = (1 << 10), + CPUCFGR_AVRP = (1 << 11), CPUCFGR_EVBARP = (1 << 12), - /* CPUCFGR_ISRP = (1 << 13), */ - /* CPUCFGR_AECSRP = (1 << 14), */ + CPUCFGR_ISRP = (1 << 13), + CPUCFGR_AECSRP = (1 << 14), + CPUCFGR_OF64A32S = (1 << 15), }; /* DMMU configure register */ @@ -280,6 +281,8 @@ typedef struct CPUOpenRISCState { /* Fields from here on are preserved across CPU reset. */ uint32_t vr; /* Version register */ + uint32_t vr2; /* Version register 2 */ + uint32_t avr; /* Architecture version register */ uint32_t upr; /* Unit presence register */ uint32_t cpucfgr; /* CPU configure register */ uint32_t dmmucfgr; /* DMMU configure register */ |