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| author | Stafford Horne <shorne@gmail.com> | 2017-01-14 07:00:28 +0900 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-02-14 08:14:59 +1100 |
| commit | c56e3b86701501364a4756201b6a9db9454463ab (patch) | |
| tree | 2ec36a17efbf5e23b406ad00ca85e3f89b8ec941 /target/openrisc/interrupt.c | |
| parent | c40413a65eeb98d6f9eeb92544ab782c812ccc51 (diff) | |
| download | focaccia-qemu-c56e3b86701501364a4756201b6a9db9454463ab.tar.gz focaccia-qemu-c56e3b86701501364a4756201b6a9db9454463ab.zip | |
target/openrisc: Fix exception handling status registers
I am working on testing instruction emulation patches for the linux kernel. During testing I found these 2 issues: - sets DSX (delay slot exception) but never clears it - EEAR for illegal insns should point to the bad exception (as per openrisc spec) but its not This patch fixes these two issues by clearing the DSX flag when not in a delay slot and by setting EEAR to exception PC when handling illegal instruction exceptions. After this patch the openrisc kernel with latest patches boots great on qemu and instruction emulation works. Cc: qemu-trivial@nongnu.org Cc: openrisc@lists.librecores.org Signed-off-by: Stafford Horne <shorne@gmail.com> Message-Id: <20170113220028.29687-1-shorne@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/openrisc/interrupt.c')
| -rw-r--r-- | target/openrisc/interrupt.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index e43fc84ef7..a243eb2751 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -38,10 +38,17 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->flags &= ~D_FLAG; env->sr |= SR_DSX; env->epcr -= 4; + } else { + env->sr &= ~SR_DSX; } if (cs->exception_index == EXCP_SYSCALL) { env->epcr += 4; } + /* When we have an illegal instruction the error effective address + shall be set to the illegal instruction address. */ + if (cs->exception_index == EXCP_ILLEGAL) { + env->eear = env->pc; + } /* For machine-state changed between user-mode and supervisor mode, we need flush TLB when we enter&exit EXCP. */ |