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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-05-22 19:36:27 -0700 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2018-07-03 00:05:28 +0900 |
| commit | 2acaa2331b96ee92f0df213784f9b6454c3d5edc (patch) | |
| tree | 9d7ab5c3ccdb64dd7e462810e81e63571ea2f4fa /target/openrisc/sys_helper.c | |
| parent | fd992ee7e3fb12aea888744313a2869c8848ef9d (diff) | |
| download | focaccia-qemu-2acaa2331b96ee92f0df213784f9b6454c3d5edc.tar.gz focaccia-qemu-2acaa2331b96ee92f0df213784f9b6454c3d5edc.zip | |
target/openrisc: Reduce tlb to a single dimension
While we had defines for *_WAYS, we didn't define more than 1. Reduce the complexity by eliminating this unused dimension. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/sys_helper.c')
| -rw-r--r-- | target/openrisc/sys_helper.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 9b4339b34e..7f458b0d17 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -86,14 +86,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.dtlb[0][idx].mr = rb; + env->tlb.dtlb[idx].mr = rb; break; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - env->tlb.dtlb[0][idx].tr = rb; + env->tlb.dtlb[idx].tr = rb; break; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -105,14 +105,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.itlb[0][idx].mr = rb; + env->tlb.itlb[idx].mr = rb; break; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - env->tlb.itlb[0][idx].tr = rb; + env->tlb.itlb[idx].tr = rb; break; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ @@ -244,11 +244,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); - return env->tlb.dtlb[0][idx].mr; + return env->tlb.dtlb[idx].mr; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - return env->tlb.dtlb[0][idx].tr; + return env->tlb.dtlb[idx].tr; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -260,11 +260,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); - return env->tlb.itlb[0][idx].mr; + return env->tlb.itlb[idx].mr; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - return env->tlb.itlb[0][idx].tr; + return env->tlb.itlb[idx].tr; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ |