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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-08-25 15:23:42 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:51:19 -0700 |
| commit | 8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2 (patch) | |
| tree | 91f063efef1666667185b148b2a33259783f37d8 /target/openrisc/sys_helper.c | |
| parent | c7efab4fc1fe5092136305a2cae67fca03f4f9c5 (diff) | |
| download | focaccia-qemu-8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2.tar.gz focaccia-qemu-8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2.zip | |
target/openrisc: Add VR2 and AVR special processor registers
Update the CPUCFG bits to arch v1.3. Include support for AVRP for cpu "any". Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/sys_helper.c')
| -rw-r--r-- | target/openrisc/sys_helper.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index a2b1f52294..cf8e637b08 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -210,6 +210,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(0, 4): /* IMMUCFGR */ return env->immucfgr; + case TO_SPR(0, 9): /* VR2 */ + return env->vr2; + + case TO_SPR(0, 10): /* AVR */ + return env->avr; + case TO_SPR(0, 11): /* EVBAR */ return env->evbar; |