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authorRichard Henderson <richard.henderson@linaro.org>2019-08-26 15:10:10 -0700
committerRichard Henderson <richard.henderson@linaro.org>2019-09-04 12:58:55 -0700
commita465772eea8fef59bef9a9fe424b1af4866991f5 (patch)
tree67872aa23218d239cfbd37c28b538d3ae063ea1f /target/openrisc/sys_helper.c
parent2b13b4b93dc924a139d7a9350cd13c2c9479d03b (diff)
downloadfocaccia-qemu-a465772eea8fef59bef9a9fe424b1af4866991f5.tar.gz
focaccia-qemu-a465772eea8fef59bef9a9fe424b1af4866991f5.zip
target/openrisc: Implement move to/from FPCSR
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/sys_helper.c')
-rw-r--r--target/openrisc/sys_helper.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index cf8e637b08..d9fe6c5948 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -37,8 +37,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
     CPUState *cs = env_cpu(env);
     target_ulong mr;
     int idx;
+#endif
 
     switch (spr) {
+#ifndef CONFIG_USER_ONLY
     case TO_SPR(0, 11): /* EVBAR */
         env->evbar = rb;
         break;
@@ -179,10 +181,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
         }
         cpu_openrisc_timer_update(cpu);
         break;
-    default:
+#endif
+
+    case TO_SPR(0, 20): /* FPCSR */
+        cpu_set_fpcsr(env, rb);
         break;
     }
-#endif
 }
 
 target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
@@ -193,8 +197,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
     OpenRISCCPU *cpu = env_archcpu(env);
     CPUState *cs = env_cpu(env);
     int idx;
+#endif
 
     switch (spr) {
+#ifndef CONFIG_USER_ONLY
     case TO_SPR(0, 0): /* VR */
         return env->vr;
 
@@ -303,11 +309,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
     case TO_SPR(10, 1): /* TTCR */
         cpu_openrisc_count_update(cpu);
         return cpu_openrisc_count_get(cpu);
+#endif
 
-    default:
-        break;
+    case TO_SPR(0, 20): /* FPCSR */
+        return env->fpcsr;
     }
-#endif
 
     /* for rd is passed in, if rd unchanged, just keep it back.  */
     return rd;