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| author | Stafford Horne <shorne@gmail.com> | 2017-04-15 07:25:32 +0900 |
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| committer | Stafford Horne <shorne@gmail.com> | 2017-05-04 09:39:01 +0900 |
| commit | ef3f5b9e7f83262e1eaea884b0a562b9fa73859c (patch) | |
| tree | 2565480f3a429a363ab1cd5a8ba01993cb8d199c /target/openrisc/sys_helper.c | |
| parent | 461a4b944f7e036b2f6bd1fce83ad4fe09e5e2bc (diff) | |
| download | focaccia-qemu-ef3f5b9e7f83262e1eaea884b0a562b9fa73859c.tar.gz focaccia-qemu-ef3f5b9e7f83262e1eaea884b0a562b9fa73859c.zip | |
target/openrisc: add numcores and coreid support
These are used to identify the processor in SMP system. Their definition has been defined in verilog cores but it not yet part of the spec but it will be soon. The proposal for this is available: https://openrisc.io/proposals/core-identifier-and-number-of-cores Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/sys_helper.c')
| -rw-r--r-- | target/openrisc/sys_helper.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 6ba816249b..e13666bea0 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -233,6 +233,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ return env->esr; + case TO_SPR(0, 128): /* COREID */ + return 0; + + case TO_SPR(0, 129): /* NUMCORES */ + return 1; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr; |