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| author | Nicholas Piggin <npiggin@gmail.com> | 2023-08-08 13:11:14 +1000 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2023-09-06 11:19:32 +0200 |
| commit | 14192307ef6e63c9a0f3c7fe937e26bee95bc6a9 (patch) | |
| tree | 5d7a00b3ab95fd16528de5a8b0139b50d470f193 /target/ppc/cpu_init.c | |
| parent | a11e3a1582b8c0d62ae3ef0323526baf2303e44a (diff) | |
| download | focaccia-qemu-14192307ef6e63c9a0f3c7fe937e26bee95bc6a9.tar.gz focaccia-qemu-14192307ef6e63c9a0f3c7fe937e26bee95bc6a9.zip | |
target/ppc: Implement breakpoint debug facility for v2.07S
ISA v2.07S introduced the breakpoint facility based on the CIABR SPR. Implement this in TCG. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target/ppc/cpu_init.c')
| -rw-r--r-- | target/ppc/cpu_init.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 3b6ccb5ea4..18b4757faa 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5127,7 +5127,7 @@ static void register_book3s_207_dbg_sprs(CPUPPCState *env) spr_register_kvm_hv(env, SPR_CIABR, "CIABR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_ciabr, KVM_REG_PPC_CIABR, 0x00000000); } @@ -7159,6 +7159,7 @@ static void ppc_cpu_reset_hold(Object *obj) env->nip = env->hreset_vector | env->excp_prefix; if (tcg_enabled()) { + cpu_breakpoint_remove_all(s, BP_CPU); if (env->mmu_model != POWERPC_MMU_REAL) { ppc_tlb_invalidate_all(env); } @@ -7346,6 +7347,8 @@ static const struct TCGCPUOps ppc_tcg_ops = { .cpu_exec_exit = ppc_cpu_exec_exit, .do_unaligned_access = ppc_cpu_do_unaligned_access, .do_transaction_failed = ppc_cpu_do_transaction_failed, + .debug_excp_handler = ppc_cpu_debug_excp_handler, + .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ |