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| author | Nicholas Miehlbradt <nicholas@linux.ibm.com> | 2022-12-20 04:23:29 +0000 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-12-21 14:17:55 -0300 |
| commit | 395b5d5b455ac3f6ebf9534454b7187a1d6118a4 (patch) | |
| tree | 7a4413290f12bb03683a3ba04bb500420fcddb57 /target/ppc/cpu_init.c | |
| parent | 320c5ad8fffe8ce7562fcc34975398bb4bb50666 (diff) | |
| download | focaccia-qemu-395b5d5b455ac3f6ebf9534454b7187a1d6118a4.tar.gz focaccia-qemu-395b5d5b455ac3f6ebf9534454b7187a1d6118a4.zip | |
target/ppc: Implement the DEXCR and HDEXCR
Define the DEXCR and HDEXCR as special purpose registers. Each register occupies two SPR indicies, one which can be read in an unprivileged state and one which can be modified in the appropriate priviliged state, however both indicies refer to the same underlying value. Note that the ISA uses the abbreviation UDEXCR in two different contexts: the userspace DEXCR, the SPR index which can be read from userspace (implemented in this patch), and the ultravisor DEXCR, the equivalent register for the ultravisor state (not implemented). Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221220042330.2387944-2-nicholas@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target/ppc/cpu_init.c')
| -rw-r--r-- | target/ppc/cpu_init.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 95d25856a0..abee71d407 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5727,6 +5727,30 @@ static void register_power10_hash_sprs(CPUPPCState *env) hashpkeyr_initial_value); } +static void register_power10_dexcr_sprs(CPUPPCState *env) +{ + spr_register(env, SPR_DEXCR, "DEXCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0); + + spr_register(env, SPR_UDEXCR, "DEXCR", + &spr_read_dexcr_ureg, SPR_NOACCESS, + &spr_read_dexcr_ureg, SPR_NOACCESS, + 0); + + spr_register_hv(env, SPR_HDEXCR, "HDEXCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0); + + spr_register(env, SPR_UHDEXCR, "HDEXCR", + &spr_read_dexcr_ureg, SPR_NOACCESS, + &spr_read_dexcr_ureg, SPR_NOACCESS, + 0); +} + /* * Initialize PMU counter overflow timers for Power8 and * newer Power chips when using TCG. @@ -6402,6 +6426,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power8_rpr_sprs(env); register_power9_mmu_sprs(env); register_power10_hash_sprs(env); + register_power10_dexcr_sprs(env); /* FIXME: Filter fields properly based on privilege level */ spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, |