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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-03 10:00:35 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-03 10:00:35 +0100 |
| commit | a97978bcc2d1f650c7d411428806e5b03082b8c7 (patch) | |
| tree | 29f81b0392e3b87dfa81c5ef10849225307d60bc /target/ppc/cpu_init.c | |
| parent | 8e6dad2028d01b7f9ec76cf3b83457fab57fa1eb (diff) | |
| parent | eba3c766fe355a4e593c1ee6944770f80b68acad (diff) | |
| download | focaccia-qemu-a97978bcc2d1f650c7d411428806e5b03082b8c7.tar.gz focaccia-qemu-a97978bcc2d1f650c7d411428806e5b03082b8c7.zip | |
Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.1-20210603' into staging
ppc patch queue 2021-06-03 Next batch of ppc target patches. Highlights are: * A fix for a regression with single-step mode * Start of moving ppc to use decodetree * Implementation of some POWER10 64-bit prefixed instructions * Several cleanups to softmmu code * Continued progress towards allowing --disable-tcg * Fix for the POWER PEF implementation * Fix for LPCR handling of hotplugged CPUs * Assorted other bugfixes and cleanups This patchset does contain a couple of changes to code outside my normal scope of maintainership, related to the removal of cpu_dump and cpu_statistics hooks. ppc was the last target arch implementing these at all, and they didn't really do anything there either. The patches should have relevant acks. # gpg: Signature made Thu 03 Jun 2021 09:20:59 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.1-20210603: (42 commits) target/ppc: fix single-step exception regression target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree target/ppc: Move addpcis to decodetree target/ppc: Implement vcfuged instruction target/ppc: Implement cfuged instruction target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions target/ppc: Implement prefixed integer store instructions target/ppc: Move D/DS/X-form integer stores to decodetree target/ppc: Implement prefixed integer load instructions target/ppc: Move D/DS/X-form integer loads to decodetree target/ppc: Implement PNOP target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI target/ppc: Add infrastructure for prefixed insns target/ppc: Move page crossing check to ppc_tr_translate_insn target/ppc: Introduce macros to check isa extensions target/ppc: powerpc_excp: Consolidade TLB miss code target/ppc: powerpc_excp: Remove dump_syscall_vectored target/ppc: powerpc_excp: Move lpes code to where it is used target/ppc: overhauled and moved logic of storing fpscr target/ppc: removed all mentions to PPC_DUMP_CPU ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/ppc/cpu_init.c')
| -rw-r--r-- | target/ppc/cpu_init.c | 216 |
1 files changed, 3 insertions, 213 deletions
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 7bdb443114..d0411e7302 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -43,7 +43,6 @@ #include "fpu/softfloat.h" #include "qapi/qapi-commands-machine-target.h" -#include "exec/helper-proto.h" #include "helper_regs.h" #include "internal.h" #include "spr_tcg.h" @@ -1206,15 +1205,12 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, /* TLB assist registers */ /* XXX : not implemented */ for (i = 0; i < 8; i++) { - void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = - &spr_write_generic32; - if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { - uea_write = &spr_write_generic; - } if (mas_mask & (1 << i)) { spr_register(env, mas_sprn[i], mas_names[i], SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, uea_write, + &spr_read_generic, + (i == 2 && (env->insns_flags & PPC_64B)) + ? &spr_write_generic : &spr_write_generic32, 0x00000000); } } @@ -8545,45 +8541,6 @@ static void init_ppc_proc(PowerPCCPU *cpu) } } -#if defined(PPC_DUMP_CPU) -static void dump_ppc_sprs(CPUPPCState *env) -{ - ppc_spr_t *spr; -#if !defined(CONFIG_USER_ONLY) - uint32_t sr, sw; -#endif - uint32_t ur, uw; - int i, j, n; - - printf("Special purpose registers:\n"); - for (i = 0; i < 32; i++) { - for (j = 0; j < 32; j++) { - n = (i << 5) | j; - spr = &env->spr_cb[n]; - uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; - ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; -#if !defined(CONFIG_USER_ONLY) - sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS; - sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS; - if (sw || sr || uw || ur) { - printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n", - (i << 5) | j, (i << 5) | j, spr->name, - sw ? 'w' : '-', sr ? 'r' : '-', - uw ? 'w' : '-', ur ? 'r' : '-'); - } -#else - if (uw || ur) { - printf("SPR: %4d (%03x) %-8s u%c%c\n", - (i << 5) | j, (i << 5) | j, spr->name, - uw ? 'w' : '-', ur ? 'r' : '-'); - } -#endif - } - } - fflush(stdout); - fflush(stderr); -} -#endif static void ppc_cpu_realize(DeviceState *dev, Error **errp) { @@ -8620,172 +8577,6 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp) pcc->parent_realize(dev, errp); -#if defined(PPC_DUMP_CPU) - { - CPUPPCState *env = &cpu->env; - const char *mmu_model, *excp_model, *bus_model; - switch (env->mmu_model) { - case POWERPC_MMU_32B: - mmu_model = "PowerPC 32"; - break; - case POWERPC_MMU_SOFT_6xx: - mmu_model = "PowerPC 6xx/7xx with software driven TLBs"; - break; - case POWERPC_MMU_SOFT_74xx: - mmu_model = "PowerPC 74xx with software driven TLBs"; - break; - case POWERPC_MMU_SOFT_4xx: - mmu_model = "PowerPC 4xx with software driven TLBs"; - break; - case POWERPC_MMU_SOFT_4xx_Z: - mmu_model = "PowerPC 4xx with software driven TLBs " - "and zones protections"; - break; - case POWERPC_MMU_REAL: - mmu_model = "PowerPC real mode only"; - break; - case POWERPC_MMU_MPC8xx: - mmu_model = "PowerPC MPC8xx"; - break; - case POWERPC_MMU_BOOKE: - mmu_model = "PowerPC BookE"; - break; - case POWERPC_MMU_BOOKE206: - mmu_model = "PowerPC BookE 2.06"; - break; - case POWERPC_MMU_601: - mmu_model = "PowerPC 601"; - break; -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - mmu_model = "PowerPC 64"; - break; -#endif - default: - mmu_model = "Unknown or invalid"; - break; - } - switch (env->excp_model) { - case POWERPC_EXCP_STD: - excp_model = "PowerPC"; - break; - case POWERPC_EXCP_40x: - excp_model = "PowerPC 40x"; - break; - case POWERPC_EXCP_601: - excp_model = "PowerPC 601"; - break; - case POWERPC_EXCP_602: - excp_model = "PowerPC 602"; - break; - case POWERPC_EXCP_603: - excp_model = "PowerPC 603"; - break; - case POWERPC_EXCP_603E: - excp_model = "PowerPC 603e"; - break; - case POWERPC_EXCP_604: - excp_model = "PowerPC 604"; - break; - case POWERPC_EXCP_7x0: - excp_model = "PowerPC 740/750"; - break; - case POWERPC_EXCP_7x5: - excp_model = "PowerPC 745/755"; - break; - case POWERPC_EXCP_74xx: - excp_model = "PowerPC 74xx"; - break; - case POWERPC_EXCP_BOOKE: - excp_model = "PowerPC BookE"; - break; -#if defined(TARGET_PPC64) - case POWERPC_EXCP_970: - excp_model = "PowerPC 970"; - break; -#endif - default: - excp_model = "Unknown or invalid"; - break; - } - switch (env->bus_model) { - case PPC_FLAGS_INPUT_6xx: - bus_model = "PowerPC 6xx"; - break; - case PPC_FLAGS_INPUT_BookE: - bus_model = "PowerPC BookE"; - break; - case PPC_FLAGS_INPUT_405: - bus_model = "PowerPC 405"; - break; - case PPC_FLAGS_INPUT_401: - bus_model = "PowerPC 401/403"; - break; - case PPC_FLAGS_INPUT_RCPU: - bus_model = "RCPU / MPC8xx"; - break; -#if defined(TARGET_PPC64) - case PPC_FLAGS_INPUT_970: - bus_model = "PowerPC 970"; - break; -#endif - default: - bus_model = "Unknown or invalid"; - break; - } - printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n" - " MMU model : %s\n", - object_class_get_name(OBJECT_CLASS(pcc)), - pcc->pvr, pcc->msr_mask, mmu_model); -#if !defined(CONFIG_USER_ONLY) - if (env->tlb.tlb6) { - printf(" %d %s TLB in %d ways\n", - env->nb_tlb, env->id_tlbs ? "splitted" : "merged", - env->nb_ways); - } -#endif - printf(" Exceptions model : %s\n" - " Bus model : %s\n", - excp_model, bus_model); - printf(" MSR features :\n"); - if (env->flags & POWERPC_FLAG_SPE) { - printf(" signal processing engine enable" - "\n"); - } else if (env->flags & POWERPC_FLAG_VRE) { - printf(" vector processor enable\n"); - } - if (env->flags & POWERPC_FLAG_TGPR) { - printf(" temporary GPRs\n"); - } else if (env->flags & POWERPC_FLAG_CE) { - printf(" critical input enable\n"); - } - if (env->flags & POWERPC_FLAG_SE) { - printf(" single-step trace mode\n"); - } else if (env->flags & POWERPC_FLAG_DWE) { - printf(" debug wait enable\n"); - } else if (env->flags & POWERPC_FLAG_UBLE) { - printf(" user BTB lock enable\n"); - } - if (env->flags & POWERPC_FLAG_BE) { - printf(" branch-step trace mode\n"); - } else if (env->flags & POWERPC_FLAG_DE) { - printf(" debug interrupt enable\n"); - } - if (env->flags & POWERPC_FLAG_PX) { - printf(" inclusive protection\n"); - } else if (env->flags & POWERPC_FLAG_PMM) { - printf(" performance monitor mark\n"); - } - if (env->flags == POWERPC_FLAG_NONE) { - printf(" none\n"); - } - printf(" Time-base/decrementer clock source: %s\n", - env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock"); - dump_ppc_insns(env); - dump_ppc_sprs(env); - fflush(stdout); - } -#endif return; unrealize: @@ -9311,7 +9102,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = ppc_cpu_class_by_name; cc->has_work = ppc_cpu_has_work; cc->dump_state = ppc_cpu_dump_state; - cc->dump_statistics = ppc_cpu_dump_statistics; cc->set_pc = ppc_cpu_set_pc; cc->gdb_read_register = ppc_cpu_gdb_read_register; cc->gdb_write_register = ppc_cpu_gdb_write_register; |