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| author | Suraj Jitindar Singh <sjitindarsingh@gmail.com> | 2019-11-28 14:46:55 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:39:48 +1100 |
| commit | 5cc7e69f6da5c52a0ac9f48ace40caf91fce807d (patch) | |
| tree | c8444b7abf282c8079f2b5eb4ccaa6f58b80e297 /target/ppc/timebase_helper.c | |
| parent | 5d62725b2fefd59abf7225d620f7092fd34b8e11 (diff) | |
| download | focaccia-qemu-5cc7e69f6da5c52a0ac9f48ace40caf91fce807d.tar.gz focaccia-qemu-5cc7e69f6da5c52a0ac9f48ace40caf91fce807d.zip | |
target/ppc: Work [S]PURR implementation and add HV support
The Processor Utilisation of Resources Register (PURR) and Scaled Processor Utilisation of Resources Register (SPURR) provide an estimate of the resources used by the thread, present on POWER7 and later processors. Currently the [S]PURR registers simply count at the rate of the timebase. Preserve this behaviour but rework the implementation to store an offset like the timebase rather than doing the calculation manually. Also allow hypervisor write access to the register along with the currently available read access. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ clg: rebased on current ppc tree ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191128134700.16091-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/timebase_helper.c')
| -rw-r--r-- | target/ppc/timebase_helper.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 8c3c2fe67c..2395295b77 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -55,6 +55,11 @@ target_ulong helper_load_purr(CPUPPCState *env) { return (target_ulong)cpu_ppc_load_purr(env); } + +void helper_store_purr(CPUPPCState *env, target_ulong val) +{ + cpu_ppc_store_purr(env, val); +} #endif target_ulong helper_load_601_rtcl(CPUPPCState *env) |