diff options
| author | Nicholas Piggin <npiggin@gmail.com> | 2023-11-23 18:02:36 +1000 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-02-23 23:24:43 +1000 |
| commit | cde2ba34a951997f01c184acf6e3a29eb6a81e79 (patch) | |
| tree | 340ee414749fc39e8cc3eca9acb0e2d35414d3db /target/ppc | |
| parent | de3ba0cc38ffb96265f29c2399df0a5c0f301f40 (diff) | |
| download | focaccia-qemu-cde2ba34a951997f01c184acf6e3a29eb6a81e79.tar.gz focaccia-qemu-cde2ba34a951997f01c184acf6e3a29eb6a81e79.zip | |
ppc/pnv: Implement the ChipTOD to Core transfer
One of the functions of the ChipTOD is to transfer TOD to the Core (aka PC - Pervasive Core) timebase facility. The ChipTOD can be programmed with a target address to send the TOD value to. The hardware implementation seems to perform this by sending the TOD value to a SCOM address. This implementation grabs the core directly and manipulates the timebase facility state in the core. This is a hack, but it works enough for now. A better implementation would implement the transfer to the PnvCore xscom register and drive the timebase state machine from there. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/cpu.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 16baea609c..0e932838aa 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1184,6 +1184,13 @@ DEXCR_ASPECT(NPHIE, 5) DEXCR_ASPECT(PHIE, 6) /*****************************************************************************/ +/* PowerNV ChipTOD and TimeBase State Machine */ +struct pnv_tod_tbst { + int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */ + int tod_sent_to_tb; /* chiptod sent TOD to the core TB */ +}; + +/*****************************************************************************/ /* The whole PowerPC CPU context */ /* @@ -1258,6 +1265,12 @@ struct CPUArchState { uint32_t tlb_need_flush; /* Delayed flush needed */ #define TLB_NEED_LOCAL_FLUSH 0x1 #define TLB_NEED_GLOBAL_FLUSH 0x2 + +#if defined(TARGET_PPC64) + /* PowerNV chiptod / timebase facility state. */ + /* Would be nice to put these into PnvCore */ + struct pnv_tod_tbst pnv_tod_tbst; +#endif #endif /* Other registers */ |